The present invention relates to a semiconductor integrated circuit device having a plurality of MOS field-effect transistors and bipolar transistors and its applied circuit device, and more particularly to a hardware arrangement of a current-driven type signal interface for speeding up the signal interface and a carry propagation device having a hardware arrangement applied thereto.
As the hardware arrangement for speeding up a signal interface, which is comprised of a semiconductor integrated circuit device having a plurality of MOS field-effect transistors and bipolar transistors integrated thereon, a BiCMOS tri-state buffer circuit has been disclosed in JP-A-59-28726. The speed-up concept of this circuit is to amplify the current of the CMOS circuit through the effect of the bipolar transistors for enhancing the driving capability of a load and driving the load at a higher speed.
In addition, as an example, a current-driven circuit applied to a wiring driver and a receiver connecting for effecting interconnection of the LSI blocks has been disclosed in JP-A-61-20346.
The foregoing prior arts have the same signal amplitude as a voltage difference between a supply voltage and a grounding voltage, such as, used in a CMOS circuit. Since the signal amplitude is large, therefore, a large amount of charges to be charged or discharged is needed for inverting the signal. This puts a limitation to speeding up the circuit. Further, since the signal amplitude is large, the larger amount of current flows through the circuit within a unit time. This results in causing more noise.
The problems associated with the prior arts have will be described in detail with reference to FIGS. 19A to 19B. FIGS. 19A to 19B show a tri-state output buffer circuit and an input circuit used for the interface between logic blocks, respectively. In FIG. 19A, 201 is an input terminal. Numeral 202 is an enable terminal. When the voltage of the terminal 202 is at a high logical level "H", the output of the circuit has a high impedance. When it is at a low logical level "L", the circuit outputs an inversion signal of the input signal at the terminal 201. The output circuit has such a fundamental concept that the logic circuit is comprised of MOS transistors and the current is amplified with bipolar transistors for driving the heavy load depending on the wiring and fan-out at a high speed. The output circuit can supply a signal whose amplitude is substantially the same as that of the CMOS circuit, that is, the potential difference between a power supply potential 1 and a grounding potential 2. More strictly, the amplitude V of the output signal of such a circuit can be derived as V=VDD-GND-2Vbe, wherein VDD is a power supply potential, GND is a grounding potential, and Vbe is a potential between a base and an emitter of the bipolar transistors 203 and 204. As an example, VDD=5 V, GND=0 V and Vbe=0.7 V are referred. In this example, the amplitude of the output signal is V=3.6 V. That is, since the signal amplitude has such a high value as V=3.6, the foregoing problems may be brought about.
FIG. 20 shows a conventional BiCMOS I/O circuit. A BiCMOS output circuit 211, a CMOS output circuit 212 and a BiCMOS input circuit 213 are connected through a bus 214. When an input terminal 202 is at "L" and an input terminal 215 is at "L", the BiCMOS output circuit 211 is selected so that the output of the CMOS output circuit 212 has a high impedance. At this condition, the bus 214 is at 0 V or 3.6 V depending on the state of the input terminal 201. When the input terminal 202 is at "H" and the input terminal 215 is at "H", the CMOS output circuit 212 is selected so that the output of the BiCMOS output circuit 211 has a high impedance. In this condition, the bus is at 0 V or 5 V depending on the state of the input terminal 216. As mentioned above, the conventional circuit provides such a high signal amplitude of the bus as 5 V or 3.6 V.
The conventional data processing apparatus employs a semiconductor element with a high-speed operating capability. This is not fast enough to process a signal at high speed. The main factor greatly controlling the performance of such a data processing apparatus is a carry delay in an adder. As a word length of the input data is made longer, the carry delay of the adder is increased linearly. To improve such a delay, a proposal has been made that a carry of each stage is calculated in parallel. Such an improved method, which is well known, is described in "Principles of CMOS VLSI Design: A Systems Perspective", by Neil H. E. Weste and Kamran Eshraghian, published 1985.
In the writing, an i-th carry Ci is represented by the following expression. EQU Ci=Gi+Pi.multidot.Ci-1 (1)
wherein EQU Gi=Ai.multidot.Bi (Generation Signal) (2) EQU Pi=Ai.sym.Bi (Propagation Signal) (3)
The expansion of those expressions results in obtaining the following expression. EQU Ci=Gi+Pi.multidot.Gi-1+Pi.multidot.Pi-1.multidot.Gi-2+ . . . +Pi.multidot.Pi-1 . . . P1.multidot.C0 (4)
The sum Si can be generated by the following expression. ##EQU1## For the first four gates, the terms indicated below can be obtained. EQU C.sub.1 =G.sub.1 +P.sub.1 C.sub.0 ( 6) EQU C.sub.2 =G.sub.2 +P.sub.2 G.sub.1 +P.sub.2 P.sub.1 C.sub.0 ( 7) EQU C.sub.3 =G.sub.3 +P.sub.3 G.sub.2 +P.sub.3 P.sub.2 G.sub.11 +P.sub.3 P.sub.2 P.sub.1 C.sub.0 ( 8) EQU C.sub.4 =G.sub.4 +P.sub.4 G.sub.3 +P.sub.4 P.sub.3 G.sub.2 +P.sub.4 P.sub.3 P.sub.2 C.sub.1 +P.sub.4 P.sub.3 P.sub.2 P.sub.1 C.sub.0 ( 9)
With respect to C.sub.4, the expression of C.sub.4 can be represented by the following expression. EQU C.sub.4 =G.sub.4 .multidot.P.sub.4 .multidot.(G.sub.3 +P.sub.3 .multidot.(G.sub.2 +P.sub.2 .multidot.(G.sub.1 +P.sub.1 .multidot.C.sub.0))) (10)
As one example of a circuit for realizing the foregoing operational expression, a Manchester carry adder shown in FIG. 27 has been known. This adder is arranged as a Manchester carry propagating circuit composed of MOS transistors only. When each MOS transistor operates on a clock signal, the transistor at an output stage changes between 0 V and 5 V. That is, the amplitude of the propagation signal is so large as to restrict the speed-up of the signal processing. Further, in this circuit, when the clock signal CK is at a logic "0", the node is pre-charged so that the output C4 is fixed at a logic "0". When the clock signal CK is at a logic "1", depending on the logic condition, the charges are discharged from the node for defining the output C4. This means that the signal is allowed to be propagated only when the clock signal CK remains at "1".
To improve this disadvantage, as described in JP-A-61-194529, there has been proposed a carry propagating device arranged to have bipolar transistors and CMOS transistors in combination. As shown in FIG. 28, this device is arranged to have a Manchester carry propagating circuit composed of the MOS transistors only and a sensing circuit composed of a bipolar transistor. The output signal of the Manchester carry propagating circuit is applied to between a base and an emitter of the bipolar transistor. Hence, the carry signal is allowed to be transmitted in the range of 0.8 V. This makes it possible to reduce the amplitude of the carry signal for speeding up the signal processing.
The prior arts, however, are designed so that the transistors may operate on a clock signal. Hence, these prior arts need a half cycle for pre-charging a node and a half cycle for determining a logic, so that the propagating period of the signal is limited to a half cycle of the clock signal. Besides, the amplitude of the carry signal cannot be limited to 0.8 V or less.